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general description the MAX2117 low-cost, direct-conversion tuner isintended for receiving mmds transmissions in the 470mhz to 1000mhz band. the MAX2117 is designed to be used in consumer set-top boxes and is compati- ble with most dvb-s demodulators. the MAX2117 directly converts the qpsk broadcast signals from the antenna to baseband using a broad- band i/q downconverter. the tuner provides differential i and q outputs to the demodulator ic. the device includes an lna and an rf variable-gain amplifier, i and q downconverting mixers, and baseband lowpass filters with programmable cutoff frequency control and digitally controlled baseband variable-gain amplifiers. together, the rf and baseband variable-gain amplifiers provide more than 80db of gain-control range. the ic is compatible with virtually all qpsk demodulators. the MAX2117 includes fully monolithic vcos, as well as a complete frequency synthesizer. additionally, an on- chip crystal oscillator is provided along with a buffered output for driving additional tuners and demodulators. synthesizer programming and device configuration are accomplished with a 2-wire serial interface. the ic fea- tures a vco autoselect (vas) function that automatically selects the proper vco. for multituner applications, the device can be configured to have one of two 2-wire interface addresses. a low-power standby mode is available whereupon the signal path is shut down while leaving the reference oscillator, digital interface, and buffer circuits active, providing a method to reduce power in single and multituner applications. the MAX2117 is the most advanced mmds tuner avail- able today. the low noise figure eliminates the need for an external lna. a small number of passive compo- nents are needed to form a complete mmds front-end solution. the tuner is available in a very small 28-pin thin qfn package. applications mmds features ? 470mhz to 1000mhz frequency range ? monolithic vco: no calibration required ? high dynamic range: -75dbm to 0dbm ? 4mhz to 40mhz integrated variable bw lp filters ? single +3.3v 5% supply ? low-power standby mode ? address pin for multituner applications ? differential i/q interface ? i 2 c 2-wire serial interface ? very small 28-pin thin qfn package MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ _____________ maxim integrated products 1 19-0986; rev 2; 5/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. vtune gndsyn cpout vcc_syn xtal vcobyp sclvcc_bb qdc- addrqdc+ idc- rfin gc1 vcc_lo + iout+qout- vcc_dig gndtune sda 19 17 16 3 5 18 4 6 vcc_vco refout 15 7 gnd iout- 20 2 vcc_rf1 21 idc+ 1 26 24 23 10 12 25 11 13 22 14 27 9 28 8 vcc_rf2 MAX2117 interface logic and control dc offset correction lpf bw control div4/div8 ep frequency synthesizer qout+ pin configuration/ functional diagram ordering information part temp range pin-package MAX2117cti+ 0c to +70c 28 thin qfn-ep* * ep = exposed paddle. + denotes a lead(pb)-free/rohs-compliant package. evaluation kit available downloaded from: http:///
complete, direct-conversion tuner for mmds applications 2 __________________________________________________ _____________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +3.9v all other pins to gnd.................................-0.3v to (v cc + 0.3v) rf input power: rfin .....................................................+10dbm vcobyp, cpout, refout, xtal, iout_, qout_, idc_, and qdc_ short-circuit protection.............................................10s continuous power dissipation (t a = +70c) 28-pin thin qfn (derated 34.5mw/c above +70c)........2.75w operating temperature range...............................0c to +70c junction temperature ......................................................+150c storage temperature range .............................-65c to +160c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c dc electrical characteristics (MAX2117 evaluation kit: v cc = +3.13v to +3.47v, v gc1 = +0.5v (max gain), t a = 0c to +70c. no input signals at rf, baseband i/os are open circuited, and lo frequency = 1000mhz. default register settings except bbg[3:0] = 1011. typical values measuredat v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) parameter conditions min typ max units supply supply voltage 3.13 3.3 3.47 v receive mode, bit stby = 0 100 160 supply current standby mode, bit stby = 1 3 ma address select input (addr) digital input-voltage high, v ih 2.4 v digital input-voltage low, v il 0.5 v digital input-current high, i ih 50 a digital input-current low, i il -50 a analog gain-control input (gc1) input voltage range maximum gain = 0.5v 0.5 2.7 v input bias current -50 +50 a vco tuning voltage input (vtune) input voltage range 0.4 2.3 v 2-wire serial inputs (scl, sda) clock frequency 400 khz input logic-level high 0.7 x v cc v input logic-level low 0.3 x v cc v input leakage current digital inputs = gnd or v cc 0.1 1 a 2-wire serial output (sda) output logic-level low i sink = 1ma 0.4 v caution! esd sensitive device MAX2117 downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ____________________________________ 3 ac electrical characteristics (MAX2117 evaluation kit: v cc = +3.13v to +3.47v, v gc1 = +0.5v (max gain), t a = 0c to +70c. default register settings except bbg[3:0] = 1011. typical values measured at v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) parameter conditions min typ max units main signal path performance input frequency range (note 2) 470 1000 mhz rf gain-control range (gc1) 0.5v < v gc1 < 2.7v 65 73 db baseband gain-control range bits gc2 = 1111 to 0000 13 15 db in-band input ip3 (note 3) +2 dbm out-of-band input ip3 (note 4) +15 dbm input ip2 (note 5) +40 dbm adjacent channel protection (note 6) 25 db v gc1 is set to 0.5v (maximum rf gain) and bbg[3:0] is adjusted to give a 1v p-p baseband output level for a -75dbm cw input tone at 1000mhz 8 noise figure starting with the same bbg[3:0] setting as above, v gc1 is adjusted to back off rf gain by 10db (note 7) 91 2 db minimum rf input return loss 470mhz < f rf < 1000mhz, in 75 system 12 db baseband output characteristics nominal output voltage swing r load = 2k //10pf 0.5 1 v p-p i/q amplitude imbalance measured at 500khz; filter set to 22.27mhz 1 db i/q quadrature phase imbalance measured at 500khz; filter set to 22.27mhz 3.5 degrees single-ended i/q outputimpedance real z o , from 1mhz to 40mhz 30 output 1db compression voltage differential 3 v p-p baseband highpass -3db frequency corner 47nf capacitors at idc_, qdc_ 400 hz baseband lowpass filters filter bandwidth range 4 40 mhz rejection ratio at 2 x f -3db 39 db group delay up to 1db bandwidth 37 ns ratio of in-filter-band to out-of-filter-band noise f inband = 100hz to 22.5mhz, f outband = 87.5mhz to 112.5mhz 25 db frequency synthesizer rf-divider frequency range 470 1000 mhz rf-divider range (n) 235 1000 reference-divider frequencyrange 4 30 mhz reference-divider range (r) 1 31 phase-detector comparisonfrequency 1 2 mhz downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 4 __________________________________________________ _____________________________________ ac electrical characteristics (continued) MAX2117 evaluation kit: v cc = +3.13v to +3.47v, v gc1 = +0.5v (max gain), t a = 0c to +70c. default register settings except bbg[3:0] = 1011. typical values measured at v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) parameter conditions min typ max units voltage-controlled oscillator and lo generation guaranteed lo frequencyrange t a = 0c to +70c 470 1000 mhz f offset = 10khz -84 f offset = 100khz -108 lo phase noise f offset = 1mhz -122 dbc/hz xtal/reference oscillator input and output buffer xtal oscillator frequencyrange parallel-resonance-mode crystal (note 8) 4.0 13.5 mhz input overdrive level ac-coupled sine wave input 0.5 1 2.0 v p-p xtal output-buffer dividerrange 18 xtal output voltage swing 4mhz to 30mhz, c load = 10pf 1 1.5 2 v p-p xtal output duty cycle 50 % note 1: min/max values are production tested at t a = +70c. min/max limits at t a = 0c and t a = +25c are guaranteed by design and characterization. note 2: gain-control range specifications met over this band. note 3: in-band iip3 test conditions: gc1 set to provide the nominal baseband output drive when mixing down a -23dbm tone at1000mhz to 5mhz baseband (f lo = 995mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -26dbm each are applied at 999mhz and 1000mhz. the im3 tone at 3mhz is measured at baseband, but is referred to therf input. note 4: out-of-band iip3 test conditions: gc1 set to provide nominal baseband output drive when mixing down a -23dbm tone at1000mhz to 5mhz baseband (f lo = 995mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -20dbm each are applied at 895mhz and 800mhz. the im3 tone at 5mhz is measured at baseband, but is referred to therf input. note 5: input ip2 test conditions: gc1 set to provide nominal baseband output drive when mixing down a -23dbm tone at 1000mhzto 5mhz baseband (f lo = 995mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -20dbm each are applied at 470mhz and 795mhz. the im2 tone at 5mhz is measured at baseband, but is referred to the rf input. note 6: adjacent channel protection test conditions: gc1 is set to provide the nominal baseband output drive with a 1000mhz27.5mbaud signal at -55dbm. gc2 set for mid-scale. the test signal will be set for pr = 7/8 and snr of -8.5db. an adjacent channel at 40mhz is added at -25dbm. dvb-s ber performance of 2e-4 will be maintained for the desired signal. gc2 may be adjusted for best performance. note 7: guaranteed by design and characterization at t a = +25c. note 8: see table 14 for crystal esr requirements. downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications _______________________________________________________________________________________ 5 supply current vs. supply voltage MAX2117 toc01 supply voltage (v) supply current (ma) 3.5 3.4 3.3 3.2 3.1 89 90 91 92 93 94 95 96 97 9888 3.0 3.6 t a = +70 c t a = +25 c t a = 0 c standby mode supply current vs. supply voltage MAX2117 toc02 supply voltage (v) supply current (ma) 3.5 3.4 3.3 3.2 3.1 2.400 2.500 2.600 2.700 2.800 2.9002.300 3.0 3.6 t a = +70 c t a = 0 c, +25 c supply current vs. baseband filter cutoff frequency baseband filter cutoff frequency (mhz) supply current (ma) MAX2117 toc03 4 8 12 16 20 24 28 32 36 40 84 86 88 90 92 94 96 98 100 102 104 hd3 vs. output voltage MAX2117 toc04 v out (v p-p ) baseband 3rd-order harmonic (dbc) 3.0 2.5 2.0 1.5 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10-60 1.0 3.5 quadrature phase vs. lo frequency lo frequency (mhz) quadrature phase ( ) MAX2117 toc5a 450 550 650 750 850 950 1050 86.5 87.5 88.5 89.5 90.5 91.5 92.5 93.5 f baseband = 10mhz t a = +70 c t a = 0 c t a = +25 c quadrature magnitude matching vs. lo frequency lo frequency (mhz) quadrature magnitude matching (db) MAX2117 toc5b 450 550 650 750 850 950 1050 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 f baseband = 10mhz t a = +70 c t a = 0 c t a = +25 c quadrature phase vs. baseband frequency MAX2117 toc06a baseband frequency (mhz) quadrature phase ( ) 16 12 8 4 87.5 88.5 89.5 90.5 91.5 92.5 93.586.5 02 0 t a = +70 c t a = +25 c f lo = 925mhz t a = 0 c quadrature magnitude matching vs. baseband frequency MAX2117 toc06b baseband frequency (mhz) quadrature magnitude matching (db) 16 12 8 4 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 -0.8 02 0 t a = +70 c t a = +25 c f lo = 925mhz t a = 0 c typical operating characteristics (MAX2117 evaluation kit: v cc = +3.3v, baseband output frequency = 5mhz; v gc1 = 1.2v; t a = +25c. default register settings except bbg[3:0] = 1011.) downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 6 __________________________________________________ _____________________________________ typical operating characteristics (continued) (MAX2117 evaluation kit: v cc = +3.3v, baseband output frequency = 5mhz; v gc1 = 1.2v; t a = +25c. default register settings except bbg[3:0] = 1011.) baseband filter frequency response MAX2117 toc07 baseband frequency (mhz) baseband output level (db) 60 40 20 -60 -50 -30-40 -20 -10 0 -80 -70 08 0 baseband filter highpass frequency response MAX2117 toc08 baseband frequency (mhz) baseband output level (db) 1000 -10 -8 -4-6 -2 0 2 -14 -12 100 10,000 programmed f -3db frequency vs. measured f -3db frequency MAX2117 toc09 programmed f -3db frequency (mhz) measured f -3db frequency (mhz) 40 20 15 25 30 35 510 5 10 2015 25 3530 40 45 0 04 5 lpf[7:0] = 12 + (f -3db - 4mhz) / 290khz baseband filter 3db frequency vs. temperature MAX2117 toc10 temperature ( c) baseband gain error at f -3db (db) 40 20 30 60 50 10 -0.8 -0.6 0 -0.4 -0.2 0.2 0.60.4 0.8 1.0 -1.0 07 0 normalized to t a = +25 c input power vs. v gc1 MAX2117 toc11 v gc1 (v) input power (dbm) 2.5 2.0 1.5 1.0 -60 -50 -40 -30 -20 -10 0 10 -80 -70 0.5 3.0 t a = +70 c t a = +25 c adjust bbg[3:0] for 1v p-p baseband output withp in = -75dbm and v gc1 = 0.5v noise figure vs. frequency frequency (mhz) noise figure (db) MAX2117 toc12 450 550 650 750 850 950 7.5 8.0 8.5 9.0 9.5 10.0 t a = +25 c t a = +70 c adjust bbg[3:0] for 1v p-p baseband output withp in = -75dbm and v gc1 = 0.5v downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications _______________________________________________________________________________________ 7 typical operating characteristics (continued) (MAX2117 evaluation kit: v cc = +3.3v, baseband output frequency = 5mhz; v gc1 = 1.2v; t a = +25c. default register settings except bbg[3:0] = 1011.) noise figure vs. input power input power (dbm) noise figure (db) MAX2117 toc13 -80 -70 -60 -50 -40 -30 -20 -10 0 0 10 20 30 40 50 60 70 adjust bbg[3:0] for 1v p-p baseband output with p in = -75dbm and v gc1 = 0.5v. f lo = 1000mhz out-of-band iip3 vs. input power input power (dbm) out-of-band iip3 (dbm) MAX2117 toc14 -80 -70 -60 -50 -40 -30 -20 -10 0 -30 -20 -10 0 10 20 30 see note 4 on page 4 for conditions in-band iip3 vs. input power input power (dbm) in-band iip3 (dbm) MAX2117 toc15 -80 -70 -60 -50 -40 -30 -20 -10 0 -60 -50 -40 -30 -20 -10 0 10 20 30 see note 3 on page 4 for conditions iip2 vs. input power input power (dbm) iip2 (dbm) MAX2117 toc16 -80 -70 -60 -50 -40 -30 -20 -10 0 -10 0 10 20 30 40 50 60 see note 5 on page 4 for conditions input return loss vs. frequency frequency (mhz) input return loss (db) MAX2117 toc17 450 550 650 750 850 950 1050 -25 -20 -15 -10 -5 0 v gc1 = 0.5v v gc1 = 2.7v phase noise at 10khz offset vs. channel frequency channel frequency (mhz) phase noise at 10khz offset (dbc/hz) MAX2117 toc18 450 550 650 750 850 950 1050 -95 -93 -91 -89 -87 -85 -83 -81 -79 -77 -75 downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 8 __________________________________________________ _____________________________________ pin description pin name function 1 vcc_rf2 dc power supply for lna. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 2 vcc_rf1 dc power supply for lna. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 3 gnd ground. connect to the boards ground plane for proper operation. 4 rfin wideband 75 rf input. connect to an rf source through a dc-blocking capacitor. 5 gc1 rf gain-control input. high-impedance analog input, with a 0.5v to 2.7v operating range. v gc1 = 0.5v corresponds to the maximum gain setting. 6 vcc_lo dc power supply for lo generation circuits. connect to a +3.3v low-noise supply. bypass to gndwith a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 7 vcc_vco dc power supply for vco circuits. connect to a +3.3v low-noise supply. bypass to gnd with a 1nfcapacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 8 vcobyp internal vco bias bypass. bypass to gnd with a 100nf capacitor connected as close as possible tothe pin. do not share capacitor ground vias with other ground connections. 9 vtune high-impedance vco tune input. connect the pll loop filter output directly to this pin with as shortof a connection as possible. 10 gndtune ground for vtune. connect to the pcb ground plane. 11 gndsyn ground for synthesizer. connect to the pcb ground plane. 12 cpout charge-pump output. connect this output to the pll loop filter input with the shortest connectionpossible. typical operating characteristics (continued) (MAX2117 evaluation kit: v cc = +3.3v, baseband output frequency = 5mhz; v gc1 = 1.2v; t a = +25c. default register settings except bbg[3:0] = 1011.) phase noise vs. offset frequency offset frequency (khz) phase noise (dbc/hz) MAX2117 toc19 -130 -120 -110 -100 -90 -80 -70 0.1 1 10 100 1000 f lo = 1000mhz lo leakage vs. lo frequency lo frequency (mhz) lo leakage (dbm) MAX2117 toc20 450 550 650 750 850 950 1050 -100 -95 -90 -85 -80 measured at rf input downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ____________________________________ 9 pin description (continued) pin name function 13 vcc_syn dc power supply for synthesizer circuits. connect to a +3.3v low-noise supply. bypass to gnd witha 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 14 xtal crystal-oscillator interface. use with an external parallel-resonance-mode crystal by a series 1nfcapacitor. see the typical operating circuit . 15 refout crystal-oscillator buffer output. a dc-blocking capacitor must be used when driving externalcircuitry. 16 vcc_dig dc power supply for digital logic circuits. connect to a +3.3v low-noise supply. bypass to gndwith a 1nf capacitor connected as close to the pin as possible. do not share capacitor ground vias with other ground connections. 17 qout+ 18 qout- quadrature baseband differential output. ac-couple with a 47nf capacitor to the demodulator input. 19 iout+ 20 iout- in-phase baseband differential output. ac-couple with a 47nf capacitor to the demodulator input. 21 idc+ 22 idc- i-channel baseband dc offset correction. connect a 47nf ceramic chip capacitor from idc- toidc+. 23 qdc+ 24 qdc- q-channel baseband dc offset correction. connect a 47nf ceramic chip capacitor from qdc- toqdc+. 25 vcc_bb dc power supply for baseband circuits. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 26 sda 2-wire serial-data interface. requires a 1k pullup resistor to v cc . 27 scl 2-wire serial-clock interface. requires a 1k pullup resistor to v cc . 28 addr address. must be connected to either ground (logic 0) or supply (logic 1). e p exposed paddle. solder evenly to the boards ground plane for proper operation. downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 10 _________________________________________________ _____________________________________ msb lsb data byte reg no register name read/ write reg address d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 1 n-divider msb write 0x00 x n[14] n[13] n[12] n[11] n[10] n[9] n[8] 2 n-divider lsb write 0x01 n[7] n[6] n[5] n[4] n[3] n[2] n[1] n[0] 3 charge pump write 0x02 cpmp[1] 0 cpmp[0] 0 cplin[1] 0 cplin[0] 0 x x x x 4 not used write 0x03 x x x x x x x x 5 not used write 0x04 x x x x x x x x 6 xtal divider/ r-divider write 0x05 xd[2] xd[1] xd[0] r[4] r[3] r[2] r[1] r[0] 7 pll write 0x06 d48 cps icp x x x x x 8 vco write 0x07 vco[4] vco[3] vco[2] vco[1] vco[0] vas adl ade 9 lpf write 0x08 lpf[7] lpf[6] lpf[5] lpf[4] lpf[3] lpf[2] lpf[1] lpf[0] 10 control write 0x09 stby x pwdn 0 x bbg[3] bbg[2] bbg[1] bbg[0] 11 shutdown write 0x0a x pll 0 div 0 vco 0 bb 0 rfmix 0 rfvga 0 fe 0 12 test write 0x0b cptst[2] 0 cptst[1] 0 cptst[0] 0 x turbo 1 ld mux[2] 0 ld mux[1] 0 ld mux[0] 0 13 status byte-1 read 0x0c por vasa vase ld x x x x 14 status byte-2 read 0x0d vcosbr[4] vcosbr[3] vcosbr[2] vcosbr[1] vcosbr[0] ad c[2] adc[1] adc[0] table 1. register configuration 0 = set to 0 for factory-tested operation. 1 = set to 1 for factory-tested operation. x = dont care. bit name bit location (0 = lsb) default function x 7 x dont care. n[14:8] 6C0 0000011 sets the most significant bits of the pll integer-divide number (n).default value is n = 950 decimal. n can range from 235 to 1000. table 2. n-divider msb register table 3. n-divider lsb register detailed description register description the MAX2117 includes 12 user-programmable registersand 2 read-only registers. see table 1 for register con- figurations. the register configuration of table 1 showseach bit name and the bit usage information for all regis- ters. note that all registers must be written after and no earlier than 100s after the device is powered up. bit name bit location (0 = lsb) default function n[7:0] 7C0 10110110 sets the least significant bits of the pll integer-divide number (n).default value is n = 950 decimal. n can range from 235 to 1000. downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ___________________________________ 11 bit name bit location (0 = lsb) default function cpmp[1:0] 7, 6 00 charge-pump minimum pulse width. users must program to 00upon powering up the device. cplin[1:0] 5, 4 00 controls charge-pump linearity.00 = typically balanced charge and sink currents. other values are not tested. x 3C0 x dont care. table 4. charge-pump register bit name bit location (0 = lsb) default function xd[2:0] 7, 6, 5 000 sets the crystal-divider setting.000 = divide by 1 (default) 001 = divide by 2 011 = divide by 3 100 = divide by 4 101 through 110 = all divide values from 5 (101) to 7 (110) 111 = divide by 8 r[4:0] 4C0 00100 sets the pll reference-divider (r) number.00001 = divide by 1 00010 = divide by 2 00011 = divide by 3 00100 = divide by 4 (default) 11111 = divide by 31 table 5. xtal buffer and reference-divider register bit name bit location (0 = lsb) default function d48 7 1 vco divider setting.0 = divide by 4. use for lo frequencies 563mhz. 1 = divide by 8. use for lo frequencies < 563mhz. cps 6 1 charge-pump current mode.0 = charge-pump current controlled by icp bit 1 = charge-pump current controlled by vco autoselect (vas) icp 5 0 charge-pump current.0 = 600a typical 1 = 1200a typical x 4C0 x dont care. table 6. pll register downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 12 _________________________________________________ _____________________________________ bit name bit location (0 = lsb) default function vco[4:0] 7C3 11001 controls which vco is activated when using manual vcoprogramming mode. this also serves as the starting point for the vco autoselect mode. vas 2 1 vco autoselection (vas) circuit. 0 = disable vco selection must be programmed through i 2 c 1 = enable vco selection controlled by autoselection circuit adl 1 0 enables or disables the vco tuning voltage adc latch when the vco autoselect mode (vas) is disabled. 0 = disables the adc latch 1 = latches the adc value ade 0 0 enables or disables vco tuning voltage adc read when the vcoautoselect mode (vas) is disabled. 0 = disables adc read 1 = enables adc read table 7. vco register bit name bit location (0 = lsb) default function lpf[7:0] 7C0 01001011 sets the baseband lowpass filter 3db corner frequency. 3db corner frequency = 4mhz + (lpf[7:0] - 12) x 290khz. table 8. lowpass filter register bit name bit location (0 = lsb) default function stby 7 0 software standby control.0 = normal operation 1 = disables the signal path and frequency synthesizer, leaving only the 2-wire bus, crystal oscillator, xtalout buffer, and xtalout buffer divider active x 6 x dont care. pwdn 5 0 factory use only.0 = normal operation; other value is not tested x 4 x dont care. bbg[3:0] 3C0 0000 baseband gain setting (1db typical per step).0000 = minimum gain (0db) 1111 = maximum gain (15db typical) table 9. control register downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ___________________________________ 13 table 10. shutdown register table 11. test register bit name bit location (0 = lsb) default function x 7 x dont care. pll 6 0 pll enable.0 = normal operation 1 = shuts down the pll. value not tested. div 5 0 divider enable.0 = normal operation 1 = shuts down the divider. value not tested. vco 4 0 vco enable.0 = normal operation 1 = shuts down the vco. value not tested. bb 3 0 baseband enable.0 = normal operation 1 = shuts down the baseband. value not tested. rfmix 2 0 rf mixer enable.0 = normal operation 1 = shuts down the rf mixer. value not tested. rfvga 1 0 rf vga enable.0 = normal operation 1 = shuts down the rf vga. value not tested. fe 0 0 rf front-end enable.0 = normal operation 1 = shuts down the rf front-end. value not tested. bit name bit location (0 = lsb) default function cptst[2:0] 7, 6, 5 000 charge-pump test modes.000 = normal operation (default) 001 = crystal translator ecl to cmos path 100 = both source and sink currents enabled 101 = source current enabled 110 = sink current enabled 111 = high impedance (both source and sink current disabled) x 4 x dont care. turbo 3 0 charge-pump fast lock. users must program to 1 upon poweringup the device. ldmux[2:0] 2, 1, 0 000 refout output.000 = normal operation; other values are not tested downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 14 _________________________________________________ _____________________________________ bit name bit location (0 = lsb) function por 7 power-on reset status.0 = chip status register has been read with a stop condition since last power-on 1 = power-on reset (power cycle) has occurred, default values have been loaded in registers vasa 6 indicates whether vco autoselection was successful.0 = indicates the autoselect function is disabled or unsuccessful vco selection 1 = indicates successful vco autoselection vase 5 status indicator for the autoselect function.0 = indicates the autoselect function is active 1 = indicates the autoselect process is inactive ld 4 pll lock detector. turbo bit must be programmed to 1 for valid ld reading.0 = unlocked 1 = locked x 3C0 dont care. table 12. status byte-1 register table 13. status byte-2 register bit name bit location (0 = lsb) function vcosbr[4:0] 7C3 vco band readback. adc[2:0] 2, 1, 0 vas adc output readback.000 = out of lock 001 = locked 010 = vas locked 101 = vas locked 110 = locked 111 = out of lock downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ___________________________________ 15 2-wire serial interface the MAX2117 uses a 2-wire i 2 c-compatible serial interface consisting of a serial-data line (sda) and aserial-clock line (scl). sda and scl facilitate bidirec- tional communication between the MAX2117 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl signal to permit data transfer. the MAX2117 behaves as a slave device that transfers and receives data to and from the master. sda and scl must be pulled high with external pullup resistors (1k ? or greater) for proper bus operation. pullup resistorsshould be referenced to the MAX2117s v cc . one bit is transferred during each scl clock cycle. aminimum of nine clock cycles is required to transfer a byte in or out of the MAX2117 (8 bits and an ack/nack). the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the busis not busy. start and stop conditions the master initiates a transmission with a start condi-tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit(ack) or a not-acknowledge bit (nack). both the mas- ter and the MAX2117 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the bus master must reattempt communication at a later time. slave address the MAX2117 has a 7-bit slave address that must besent to the device following a start condition to initi- ate communication. the slave address is internally pro- grammed to 1100000. the eighth bit (r/ w ) following the 7-bit address determines whether a read or writeoperation will occur. the MAX2117 continuously awaits a start condition followed by its slave address. when the device recog- nizes its slave address, it acknowledges by pulling the sda line low for one clock period; it is ready to accept or send data depending on the r/ w bit (figure 1). the write/read address is c0/c1 if the addr pin is con-nected to ground. the write/read address is c2/c3 if the addr pin is connected to v cc . write cycle when addressed with a write command, the MAX2117allows the master to write to a single register or to multi- ple successive registers. a write cycle begins with the bus master issuing a start condition followed by the seven slave address bits and a write bit (r/ w = 0). the MAX2117 issues an ack if the slave address byte is successfully received.the bus master must then send to the slave the address of the first register it wishes to write to (see table 1 for register addresses). if the slave acknowledges the address, the master can then write one byte to the regis- ter at the specified address. data is written beginning with the most significant bit. the MAX2117 again issues an ack if the data is successfully written to the register. the master can continue to write data to the successive internal registers with the MAX2117 acknowledging each successful transfer, or it can terminate transmission by issuing a stop condition. the write cycle does not termi- nate until the master issues a stop condition. scl 1 234567 1100000 89 r/w ack slave address s sda figure 1. MAX2117 slave address byte with addr pin connected to ground downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 16 _________________________________________________ _____________________________________ figure 2 illustrates an example in which registers 0through 2 are written with 0x0e, 0xd8, and 0xe1, respectively. read cycle when addressed with a read command, the MAX2117allows the master to read back a single register, or mul- tiple successive registers. a read cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the MAX2117 issues an ack if the slave address byte is successfully received. the busmaster must then send the address of the first register it wishes to read (see table 1 for register addresses). theslave acknowledges the address. then, a start condi- tion is issued by the master, followed by the 7 slave address bits and a read bit (r/ w = 1). the MAX2117 issues an ack if the slave address byte is successfullyreceived. the MAX2117 starts sending data msb first with each scl clock cycle. at the 9th clock cycle, the master can issue an ack and continue to read succes- sive registers, or the master can terminate the transmis- sion by issuing a nack. the read cycle does not terminate until the master issues a stop condition. figure 3 illustrates an example in which registers 0 through 2 are read back. write device address r/ w ack write register address ack write data to register 0x00 ack write data to register 0x01 ack write data to register 0x02 ack start 1100000 0 0x00 0x0e 0xd8 0x0e1 stop figure 2. example: write registers 0 through 2 with 0x0e, 0xd8, and 0xe1, respectively. device address r / w 1100000 register address 00000000 0 s t ar t s t ar t a c k a c k reg 02 data xxxxxxxx s t o p n a c k reg 00 data xxxxxxxx a c k reg 01 data xxxxxxxx a c k a c k device address r / w 1100000 1 figure 3. example: receive data from read registers. downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ______________________________________________________________________________________ 17 applications information the MAX2117 downconverts rf signals in the 470mhz to1000mhz range directly to the baseband i/q signals. the devices are targeted for digital dbs tuner applications. rf input the rf input of the MAX2117 is internally matched to75 . only a dc-blocking capacitor is needed. see the typical operating circuit . rf gain control the MAX2117 features a variable-gain low-noise amplifi- er providing 73db of rf gain range. the voltage-control (vgc) range is 0.5v (minimum attenuation) to 2.7v (maximum attenuation). baseband variable-gain amplifier the receiver baseband variable-gain amplifiers provide15db of gain-control range programmable in 1db steps. the vga gain can be serially programmed through the spi? interface by setting bits bbg[3:0] in the control register. baseband lowpass filter the MAX2117 includes a programmable on-chip 7th-order butterworth filter. the -3db corner frequency of the baseband filter is programmable by setting the bits lpf[7:0] in the lowpass register. the value of the lpf[7:0] is determined by the following equation: where f -3db is in units of mhz. the filter can be adjusted from approximately 4mhz to40mhz. total device supply current depends on the fil- ter bw setting, with increasing current commensurate with increasing -3db bw. dc offset cancellation the dc offset cancellation is required to maintain the i/qoutput dynamic range. connecting an external capacitor between idc+ and idc- forms a highpass filter for the i channel, and an external capacitor between qdc+ and qdc- forms a highpass filter for the q channel. keep the value of the external capacitor less than 47nf to form a typical highpass corner of 400hz. xtal oscillator the MAX2117 contains an internal reference oscillator,reference output divider, and output buffer. all that is required is to connect a crystal through a series, 1nf capacitor. to minimize parasitics, place the crystal and series capacitor as close as possible to pin 14 (xtal pin). see table 14 for crystal (xtal) esr (equivalent series resistance) requirements. the typical input capacitance is 40pf. vco autoselect (vas) the MAX2117 includes 24 vcos. the local oscillator fre-quency can be manually selected by programming the vco[4:0] bits in the vco register. the selected vco is reported in the status byte-2 register (see table 13). alternatively, the MAX2117 can be set to autonomously choose a vco by setting the vas bit in the vco regis- ter to logic-high. the vas routine is initiated once the n-divider lsb register word (reg 2) is loaded. in the event that only the r-divider register or n- divider msb register word is changed, the n-divider lsb word must also be loaded last to initiate the vco autoselect function. the vco value pro- grammed in the vco[4:0] register serves as the start-ing point for the automatic vco selection process. during the selection process, the vase bit in the status byte-1 register is cleared to indicate the autoselection function is active. upon successful completion, bits vase and vasa are set and the vco selected is reported in the status byte-2 register (see table 13). if the search is unsuccessful, vasa is cleared and vase is set. this indicates that searching has ended but no good vco has been found, and occurs when trying to tune to a frequency outside the vcos specified frequency range. refer to the MAX2117 vas application note for more information. lpf[7:0]dec = () . , fm h z mhz db + 3 4 029 12 spi is a trademark of motorola, inc. esr max ( ) xtal frequency (mhz) 150 4 < f xtal 6 100 6 < f xtal 8 40 8 < f xtal 13.5 table 14. maximum cystal esrrequirements downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications 18 _________________________________________________ _____________________________________ 3-bit adc the MAX2117 has an internal 3-bit adc connected tothe vco tune pin (vtune). this adc can be used for checking the lock status of the vcos. table 15 summarizes the adc trip points, and the vco lock indication. the vco autoselect routine only selects a vco in the vas locked range. this allows room for a vco to drift over temperature and remain in a valid locked range. the adc must first be enabled by setting the ade bit in the vco register. the adc reading is latched by a sub- sequent programming of the adc latch bit (adl = 1). the adc value is reported in the status byte-2 register (see table 13). standby mode the MAX2117 features normal operating mode andstandby mode using the i 2 c interface. setting a logic-high to the stby bit in the control registerputs the device into standby mode, during which only the 2-wire-compatible bus, the crystal oscillator, the xtal buffer, and the xtal buffer divider are active. in all cases, register settings loaded prior to entering shutdown are saved upon transition back to active mode. default register values are provided for the users convenience only. its the users responsibility to load all the registers no sooner than 100s after the device is powered up. layout considerations the MAX2117 ev kit serves as a guide for pcb layout. keep rf signal lines as short as possible to mini- mize losses and radiation. use controlled impedance on all high-frequency traces. for proper operation, the exposed paddle must be soldered evenly to the boards ground plane. use abundant vias beneath the exposed paddle for maximum heat dissipation. use abundant ground vias between rf traces to minimize undesired coupling. bypass each v cc pin to ground with a 1nf capacitor placed as close as possible to the pin. adc[2:0] lock status 000 out of lock 001 locked 010 vas locked 101 vas locked 110 locked 111 out of lock table 15. adc trip points and lock status downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications ___________________________________________________ ___________________________________ 19 chip information process: bicmos typical operating circuit vtune gndsyn cpout vcc_syn xtal vcobyp scl vcc_bb qdc- addr qdc+ idc- rfin gc1 vcc_lo + iout+ qout-vcc_dig gndtune sda 19 17 16 3 5 18 4 6 refout 15 7 vcc_rf1 iout- 20 2 vcc_rf2 21 idc+ 1 26 24 23 10 12 25 11 13 22 14 27 9 28 8 MAX2117 interface logic and control dc offset correction lpf bw control div4/div8 ep frequency synthesizer qout+ v cc v cc v cc baseband outputs serial-clock input serial-data input/output v cc v cc v cc gnd vcc_vco rf input v cc package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package draw-ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tqfn-ep t2855+3 21-0140 90-0023 downloaded from: http:///
MAX2117 complete, direct-conversion tuner for mmds applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/07 initial release 1 3/08 corrected tables 1, 6, 10, and 11; corrected electrical characteristics and typical operating characteristics global conditions; corrected noise figure spec conditions 2C8, 10, 11, 13, 19 2 5/10 added lead temperature to absolute maximum ratings ; corrected function of bit d48 in table 6 2, 11 downloaded from: http:///

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